This invention relates generally to bypass circuits and more particularly to a bypass circuit incorporating a ceramic capacitor which utilizes a buried layer.
Prior art relating to solid state capacitors includes such patents as U.S. Pat. No. 4,665,465 to Tanabe and U.S. Pat. No. 5,107,394 to Naito et al. Construction of these capacitors includes multiple electrode layers which are fastened by means of a soldering process to a mechanical end cap. A soldering process introduces a degree of unreliability as a result of residual stresses formed in a capacitor during its manufacture. Additional unreliability results from stresses which are imposed on a solder joint due to differential rates of thermal expansion and contraction of various components of the capacitor; including its electrode, its dielectric material, its solder material and its end cap; when the capacitor is exposed to temperature variations and extremes, with or without stressful influences, during use. Also relevant is U.S. Pat. No. 5,576,926 to the present Application.
It is an object of the present invention to provide a bypass circuit that is particularly effective at very high frequencies.
Another object of the invention is to provide a bypass circuit which performs with highly reliability.
Another object of the invention is to provide a bypass circuit which is capable of highly reliability over a broad range of operating temperatures.
Yet another object of the invention is to provide a bypass circuit which can be manufactured in quantity at a low unit cost while maintaining high levels of quality.
The foregoing and other objects and advantages of the invention will appear more clearly hereinafter.
In accordance with the invention there is provided a bypass circuit which includes a planar electrode layer mounted between a pair of dielectric layers. Length and width dimensions of the dielectric layers are somewhat greater than corresponding length and width dimensions of the electrode layer and the electrode layer generally is centered with respect to the dielectric layers. One layer of the pair of dielectric layers has a pair of spaced apart contact members, each having a different polarity from the other. A resistive layer is mounted onto the other dielectric layer. The contact members extend onto end portions of the dielectric layers and electrically connect to opposite ends of the resistive layer. The contact member design helps facilitate testing of the circuit. The dielectric layer which is attached to the contact member has a selected thickness which allows the dielectric layer, in combination with the electrode layer, to develop a desired value of capacitance between the contact members. Similarly, the resistive layer has a selected dimension and thickness to develop a desired value of resistance in parallel with the capacitance value.
In an alternative embodiment of the invention, the electrode layer extends outwardly to connect to one of the contact members.
In another alternative embodiment of the invention, the pair of spaced apart contact members is replaced by a pair of metallized areas (each having a different polarity from the other) and the dielectric layer in combination with the electrode layer develop a desired value of capacitance between the two metallized areas. The metallized areas facilitate mounting the bypass circuit on a circuit board while using minimum surface area of the circuit board.